<div>Thanks Gregory,Eldis, Arun and Jakub.</div> <div> </div> <div>I'm onto it... lets see how it works out.</div> <div> </div> <div> </div> <div>Saad<BR><BR><BR><B><I>Jakub Ladman <ladmanj@volny.cz></I></B> wrote:</div> <BLOCKQUOTE class=replbq style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #1010ff 2px solid">Here is the fastest mirror<BR>http://kuba.tharrrk.net/spider/<BR>Unfortunately, there is not any english version.<BR><BR>Verilog code compiled for CPLD can be compiled also for FPGA, but i have no <BR>experience with any FPGA, but its much larger capacity may be very nice.<BR>CPLDs are a little bit faster, than FPGAs, but here, where 32MHz maximal <BR>frequency is used it will be no problem.<BR><BR>Xilinx webpack gives you information about speed of the project after its <BR>compilation.<BR><BR>Jakub Ladman<BR><BR><BR>Dne Sunday 16 March 2008 02:52:13 Arun Krishnan napsal(a):<BR>> Hi.<BR>><BR>>
http://bleesmrt.hopto.org/~ladmanj/spider/<BR>><BR>> Regards,<BR>> Arun<BR>><BR>><BR>> ----- Original message -----<BR>> From: "eldis" <ELDIS111@SEZNAM.CZ><BR>> To: "Twibright Ronja" <RONJA@LISTS.POINTLESS.NET><BR>> Date: Sat, 15 Mar 2008 22:30:57 +0100<BR>> Subject: Re: [Ronja] Trying out a FPGA<BR>><BR>> Very important thing - ADC/DAC must be High-speed..<BR>> I assume, that you are talking about Spartan-IIIE Starter kit - look at<BR>> manual, it will be way too slow.<BR>><BR>> eldis<BR>><BR>> > Thanks for the info Gregory,<BR>> ><BR>> > It does have an integrated ADC/ DAC, I will discuss the possibility<BR>> > with my instructors...<BR>> ><BR>> > By the way does anyone have the link for the spider project?<BR>> ><BR>> > Thanks<BR>> ><BR>> > Saad<BR>> ><BR>> > */Gregory Maxwell <GMAXWELL@GMAIL.COM>/* wrote:<BR>> ><BR>> > On Thu, Mar 13,
2008 at 3:00 PM, Saad Shakeel<BR>> ><BR>> > wrote:<BR>> > > Hi everyone,<BR>> > ><BR>> > > Just got a SPARTAN 3-E FPGA..... and was wondering if i can<BR>> ><BR>> > implement the<BR>> ><BR>> > > some parts of the RONJA on it as well....<BR>> > > I came across the SPIDER project, which was implemented on a<BR>> ><BR>> > CPLD, but i'm<BR>> ><BR>> > > not sure if a CPLD code is compatible with an FPGA too?<BR>> ><BR>> > If you have a DAC and ADC chips you could implement the pretty much a<BR>> > complete signal chain... QAM (de)modulation on the FPGA, error<BR>> > correction, equalization, etc.<BR>> ><BR>> > A ronja type device could consist of little more than:<BR>> ><BR>> > [ethernet mac] - [fpga] - [dac] - [voltage to current amp] - [Tx LED]<BR>> > - [adc] - [preamp] - [RX sensor]<BR>> > - [small dac] / <
AGC<BR>> ><BR>> > A digital signal chain like this is, in my opinion, the most cost<BR>> > effective way to achieve speeds of 100mbit without switching to laser<BR>> > diodes.<BR>> ><BR>> > QAM 16 would should be able to fit 100mbit into the (post<BR>> > equalization) bandpass or the LEDs being used for 10mbit ronja today,<BR>> > though I do not know what the SNR is like on real paths.<BR>> ><BR>> > --<BR>> > Twibright Ronja mailing list http://ronja.twibright.com<BR>> > Ronja@lists.pointless.net<BR>> > http://pointless.net/mailman/listinfo/ronja<BR>> ><BR>> ><BR>> > ------------------------------------------------------------------------<BR>> > Looking for last minute shopping deals? Find them fast with Yahoo!<BR>> > Search.<BR>> > <HTTP: evt="51734/*http://tools.search.yahoo.com/newsearc<br" us.rd.yahoo.com>>
>h/category.php?category=shopping><BR>><BR>> --<BR>> Twibright Ronja mailing list http://ronja.twibright.com<BR>> Ronja@lists.pointless.net<BR>> http://pointless.net/mailman/listinfo/ronja<BR><BR><BR><BR>-- <BR>Twibright Ronja mailing list http://ronja.twibright.com<BR>Ronja@lists.pointless.net<BR>http://pointless.net/mailman/listinfo/ronja<BR></BLOCKQUOTE><BR><p> 
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